1. Field of the Invention
This invention generally relates to device testing. In particular, the invention relates to testing of memory arrays.
2. Description of Related Art
Testing memory devices is usually a tedious process. In addition to timing and electrical tests, logic testing is necessary to ensure that the memory devices can store data reliably.
For random access memory (RAM), either static or dynamic, the logic testing usually includes a write cycle followed by a read cycle. A known test data item is written into a specified memory location. Then the contents of the memory at that specified location are read out. The read out contents are compared with the known test data item. If they match, the logic testing is successful. If they do not match, the memory device fails the test. The test procedure is then repeated for all memory locations.
A memory array that consists of a number of memory elements may be tested in a similar manner. Memory arrays are used in a memory module or in a single-chip microcomputer (e.g., a microcontroller). However, testing memory arrays through read/write cycling as above has a number of problems. Most significantly, the testing time is long because the write and read cycles have to be performed on every memory location. For large size memory arrays, testing each memory location in such a sequential manner is undesirable.
Therefore there is a need in the technology to provide an efficient and reliable test procedure for memory arrays.